Self-Time Tracking Circuit to Improve Access Time of SRAM

We are entering in to a VLSI design era where few Pico seconds of memory access or cycle times will make a big impact on SOC designs performance. So, improving each Pico second of SRAM memory performance will lead to many design wins at the present competitive market. In SRAM memory design it’s important to see that sufficient voltage differential is created by the time sense amplifier is turned on. If not, we need to delay the sense amplifier enable signal till sufficient voltage differential is created. This minimum sense amp differential voltage requirement varies with PVT corners. Assume in order to improve sense amp differential i.e., yield at fast process corner it may require to increase the voltage difference between bit line and bit line bar at sense turn on time. It will be achieved by delaying the sense amp enable signal by few Pico seconds. But, delaying sense amp enable signal at fast process corner by few Pico seconds will pushout sense amp enable signal even more at slow process corner thereby impacting the access time of the memory. In this paper we are presenting a self-time circuit method which will improve the yield at faster process corner at the same time it will not impact the memory access time at slow process corner.